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?2002 silicon storage technology, inc. s71197-00-000 1/02 543 1 the sst logo and superflash are trademarks registered by silicon storage technology, inc. in the u.s. patent and trademark offi ce. concurrent superflash, csf, and combomemory are trademarks of silicon storage technology, inc. these specifications are subject to change without notice. preliminary information features: ? flash organization: two 1m x16 quad-bank architecture for concurrent read-while-write operation ? 12 mbit + 4 mbit + 12 mbit + 4 mbit sram organization: ? 2 mbit: 256k x8 or 128k x16 ? 4 mbit: 512k x8 or 256k x16 single 2.7-3.3v read-while-write operations superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention low power consumption: ? active current: 35 ma (typical) ? standby current: 25 a (typical) sector-erase capability ? uniform 1 kword sectors block-erase capability ? uniform 32 kword blocks read access time ? flash: 70 and 90 ns ? sram: 70 and 90 ns latched address and data fast erase and word-program: ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 70 ms (typical) ? word-program time: 14 s (typical) ? chip rewrite time: 30 seconds (typical) automatic write timing ? internal v pp generation end-of-write detection ? toggle bit ? data# polling cmos i/o compatibility jedec standard command set packages available ? 56-ball lfbga (10mm x 12mm x 1.4mm) product description the sst34hf3223b/3243b combomemory devices inte- grate four cmos flash memory banks with a 256k x8 / 128k x16 or 512k x8 / 256k x16 cmos sram memory bank in a multi-chip package (mcp). these devices are fabricated using sst?s proprietary, high-performance cmos superflash technology incorporating the split-gate cell design and thick oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. the sst34hf3223b/3243b devices are ideal for applications such as cellular phones, pdas and other portable electronic devices in a low power and small form factor system. the sst34hf3223b/3243b features multiple flash mem- ory bank architecture allowing for concurrent operations between the four flash memory banks and the sram. the devices can read data from either bank while an erase or program operation is in progress in the opposite bank. the four flash memory banks are partitioned as two 12 mbit and two 4 mbit for storing boot code, program code, config- uration/parameter data and user data. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. the sst34hf3223b/3243b devices offer a typical endurance of 100,000 cycles. data retention is rated at greater than 100 years. with high performance word- program, the flash memory banks provide a typical word- program time of 14 sec. the entire flash memory bank can be erased and programmed word-by-word in typically 30 seconds for the sst34hf3223b/3243b, when using interface features such as toggle bit or data# polling to indicate the completion of program operation. to protect against inadvertent flash write, the sst34hf3223b/3243b devices contain on-chip hardware and software data pro- tection schemes. the flash and sram operate as two independent memory banks with respective bank enable signals. the memory bank selection is done by two bank enable signals. the sram bank enable signal, bes1# and bes2, selects the sram bank. the flash memory bank enable signal, bef# (bef1# or bef2#), has to be used with software data pro- tection (sdp) command sequence when controlling the erase and program operations in the flash memory bank. the memory banks are superimposed in the same mem- ory address space where they share common address lines, data lines, we# and oe# which minimize power con- sumption and area. 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b sst34hf3223b / sst24hf3243b32 mbit concurrent superflash + 2/4 mbit sram combomemories
2 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 designed, manufactured, and tested for applications requir- ing low power and small form factor, the sst34hf3223b/ 3243b are offered in both commercial and extended tem- peratures and a small footprint package to meet board space constraint requirements. device operation the sst34hf3223b/3243b uses bes1#, bes2 and bef# (bef1# or bef2#) to control operation of either the flash or the sram memory bank. when bef# (bef1# or bef2#) is low, the flash bank is activated for read, pro- gram or erase operation. when bes1# is low, and bes2 is high the sram is activated for read and write operation. bef# (bef1# or bef2#) and bes1# cannot be at low level, and bes2 cannot be at high level at the same time. if all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. all address, data, and control lines are shared by flash and sram memory banks which minimizes power consump- tion and loading. the device goes into standby when bef# (bef1# and bef2#) and bes1# bank enables are raised to v ihc (logic high) or when bef# (bef1# and bef2#) are high and bes2 is low. concurrent read/write operation quadruple bank architecture of sst34hf3223b/3243b devices allows the concurrent read/write operation whereby the user can read from one bank while program or erase in the other bank. this operation can be used when the user needs to read system code in one bank while updating data in the other bank. see figure 1 for quad-bank memory organization. flash read operation the read operation of the sst34hf3223b/3243b is con- trolled by bef# (bef1# or bef2#) and oe#, both have to be low for the system to obtain data from the outputs. bef# (bef1# or bef2#) is used for device selection. when bef# (bef1# or bef2#) is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either bef# (bef1# or bef2#) or oe# is high. refer to the read cycle timing diagram for further details (figure 7). flash word-program operation the sst34hf3223b/3243b are programmed on a word- by-word basis. before the program operation, the memory must be erased first. the program operation consists of three steps. the first step is the three-byte load sequence for software data protection. the second step is to load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either bef# (bef1# or bef2#) or we#, whichever occurs last. the data is latched on the rising edge of either bef# (bef1# or bef2#) or we#, whichever occurs first. the third step is the internal program operation which is initi- ated after the rising edge of the fourth we# or bef# (bef1# or bef2#), whichever occurs first. the program operation, once initiated, will be completed (typically) within 10 s. see figures 8 and 9 for we# and bef# (bef1# or bef2#) controlled program operation timing diagrams and figure 22 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands issued during the internal program operation are ignored. flash sector/block-erase operation the sector/block-erase operation allows the system to erase the device on a sector-by-sector or block-by-block basis. the sst34hf3223b/3243b offer both sector-erase and block-erase mode. the sector architecture is based on uniform sector size of 1 kword. the block-erase mode is based on uniform block size of 32 kword. the sector- erase operation is initiated by executing a six-byte com- mand sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six-byte command sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. see figures 13 and 14 for timing waveforms. any commands issued during the sector- or block-erase operation are ignored. flash chip-erase operation the sst34hf3223b/3243b provide a chip-erase opera- tion, which allows the user to erase all unprotected sectors/ blocks to the ?1? state. this is useful when the device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or bef# (bef1# or bef2#), whichever occurs first. the selected flash bank, either bef1# or bef2# will complete the chip-erase operation. during the erase operation, the only valid read is toggle bit or data# polling. see table 4
preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b 3 ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 for the command sequence, figure 12 for timing diagram, and figure 25 for the flowchart. any commands issued dur- ing the chip-erase operation are ignored. flash write operation status detection the sst34hf3223b/3243b provide one hardware and two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the hardware detection uses the ready/busy# (ry/by#) pin. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a ready/busy# (ry/ by#), data# polling (dq 7 ), or toggle bit (dq 6 ) read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an errone- ous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has com- pleted the write cycle, otherwise the rejection is valid. ready/busy# (ry/by#) the sst34hf3223b/3243b includes a ready/busy# (ry/by#) output signal that applies to flash bank 2 only. during any sdp initiated operation, e.g., erase, program, cfi or id read operation, ry/by# is actively pulled low, indicating a sdp controlled operation is in progress. the status of ry/by# is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block-, or bank-erase, the ry/by# is valid after the rising edge of sixth we# or (ce#) pulse. ry/by# is an open drain output that allows several devices to be tied in parallel to v dd via an external pull-up resistor. ready/busy# is in high imped- ance whenever oe# or ce# is high or rst# is low. flash data# polling (dq 7 ) when the sst34hf3223b/3243b are in the internal pro- gram operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase opera- tion is completed, dq 7 will produce a ?1?. the data# polling (dq 7 ) is valid after the rising edge of fourth we# or (bef1# or bef2#) pulse for program operation. for sector-, block-, or chip-erase, the data# polling (dq 7 ) is valid after the rising edge of sixth we# or (bef1# or bef2#) pulse. see figure 10 for data# polling (dq 7 ) timing diagram and figure 23 for a flowchart. there is a 1 s bus recovery time (t br ) required before valid data can be read on the data bus. new commands can be entered immediately after dq 7 becomes true data. flash toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next opera- tion. the toggle bit (dq 6 ) is valid after the rising edge of fourth we# or (bef1# or bef2#) pulse for program opera- tion. for sector-, block- or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# or (bef1# or bef2#) pulse. see figure 11 for toggle bit timing diagram and figure 23 for a flowchart. there is a 1 s bus recovery time (t br ) required before valid data can be read on the data bus. new commands can be entered immediately after dq 6 no longer toggles. data protection the sst34hf3223b/3243b provide both hardware and software features to protect nonvolatile data from inadvert- ent writes. hardware data protection noise/glitch protection: a we# or bef# (bef1# or bef2#) pulse of less than 5 ns will not initiate a write cycle. write inhibit mode: forcing oe# low, bef# (bef1# or bef2#) high, or we# high will inhibit the write operation. this prevents inadvertent writes during power-up or power-down. hardware bloc k protection the sst34hf3223b/3243b provide a hardware block pro- tection which protects the outermost 4 kword in bank 1a. the block is protected when wp# is held low. see figure 1 for block-protection location. a user can disable block protection by driving wp# high thus allowing erase or program of data into the protected sectors. wp# must be held high prior to issuing the write command and remain stable until after the entire write operation has completed.
4 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 hardware reset (rst#) the rst# pin provides a hardware method of resetting the device to read array data. when the rst# pin is held low for at least t rp, any in-progress operation will terminate and return to read mode (see figure 19). when no internal program/erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place (see figure 18). the erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. software data protection (sdp) the sst34hf3223b/3243b provide the jedec standard software data protection scheme for all data alteration operations, i.e., program and erase. any program opera- tion requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. the sst34hf3223b/3243b are shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. during sdp command sequence, invalid com- mands will abort the device to read mode within t rc. the contents of dq 15 -dq 8 can be v il or v ih , but no other value, during any sdp command sequence. product identification the product identification mode identifies the devices as the sst34hf3223b and sst34hf3243b and manufac- turer as sst. this mode may be accessed by software operations only. the hardware device id read opera- tion, which is typically used by programmers cannot be used on this device because of the shared lines between flash and sram in the multi-chip package. therefore, application of high voltage to pin a 9 may damage this device . users may use the software product identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. for details, see tables 3 and 4 for software operation, figure 15 for the software id entry and read timing diagram and figure 24 for the id entry command sequence flowchart. product identification mode exit in order to return to the standard read mode, the soft- ware product identification mode must be exited. exit is accomplished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 17 for timing waveform and figure 24 for a flowchart. sram operation with bes1# low, bes2 and bef# (bef1# and bef2#) high, the sst34hf3223b operates as 256k x8 or 128k x16 cmos sram, and the sst34hf3243b operates as 512k x8 or 256k x16 cmos sram, with fully static opera- tion requiring no external clocks or timing strobes. the cios pin configures the sram for x8 or x16 sram opera- tion modes. the sst34hf3223b sram is mapped into the first 128 kword address space of the device, and the sst34hf3243b sram is mapped into the first 256 kword address space. when bes1#, bef# (bef1# and bef2#) are high and bes2 is low, all memory banks are deselected and the device enters standby. read and write cycle times are equal. the control signals ubs# and lbs# provide access to the upper data byte and lower data byte. see table 3 for sram read and write data byte control modes of operation. sram read the sram read operation of the sst34hf3223b/3243b is controlled by oe# and bes1#, both have to be low with we# and bes2 high for the system to obtain data from the outputs. bes1# and bes2 are used for sram bank selec- tion. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to the read cycle timing diagram, figure 4, for further details. table 1: p roduct i dentification address data manufacturer?s id 0000h 00bfh device id sst34hf3223b 0001h 2761m sst34hf3243b 0001h 2761m t1.1 543
preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b 5 ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 sram write the sram write operation of the sst34hf3223b/3243b is controlled by we# and bes1#, both have to be low, bes2 has to be high for the system to write to the sram. during the word-write operation, the addresses and data are referenced to the rising edge of bes1# or we# the fall- ing edge of bes2 whichever occur first. the write time is measured from the last falling edge of bes1# or we# or the rising edge of bes2 to the first rising edge of bes1# or we# or the falling edge of bes2. refer to the write cycle timing diagram, figures 5 and 6, for further details. 543 ill b1.0 superflash memory (bank 1) i/o buffers superflash memory (bank 2) 2 mbit or 4 mbit sram a ms - a 0 dq 15 - dq 8 dq 7 - dq 0 a ms = most significant address control logic bef2# sa lbs# ubs# we# oe# bes1# bes2 cios bef1# address buffers address buffers wp# rst# ry/by# f unctional b lock d iagram
6 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 1: 2 m egabit x 16 c oncurrent s uper f lash q uad -b ank m emory o rganization 1fffffh 1f8000h block 63 1f7fffh 1f0000h block 62 1effffh 1e8000h block 61 1e7fffh 1e0000h block 60 1dffffh 1d8000h block 59 1d7fffh 1d0000h block 58 1cffffh 1c8000h block 57 1c7fffh 1c0000h block 56 bank 2b bank 2a 1bffffh 1b8000h block 55 1b7fffh 1b0000h block 54 11ffffh 118000h block 35 117fffh 110000h block 34 10ffffh 108000h block 33 107fffh 100000h block 32 bank 1b 543 ill f01.1 bank 1a bank 1 bank 2 4 kword sector protection (four 1 kword sectors) fffffh f8000h block 31 f7fffh f0000h block 30 effffh e8000h block 29 e7fffh e0000h block 28 dffffh d8000h block 27 d7fffh d0000h block 26 block 25 block 3 block 2 block 1 block 0 cffffh c8000h c7fffh c0000h bffffh b8000h b7fffh b0000h 1ffffh 18000h 17fffh 10000h 00ffffh 008000h 007fffh 001000h 000000h affffh a8000h block 24 block 23 block 22 block 21
preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b 7 ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 2: p in a ssignments for 56- ball lfbga (10 mm x 12 mm ) figure 3: p in a ssignments for 56- ball lfbga (10 mm x 12 mm ) a pply to future sst34hf322 x /324 x note: please refer to application note, design-in sst34hf3223a/3243a/3223b/3243b devices , to achieve drop- in replacement when sst34hf322x/324x/328x becomes available. 543 ill f02.2 a11 a8 we# wp# lbs# a7 a15 a12 a19 bes2 rst# ubs# a6 a3 bef1# a13 a9 nc ry/by# a18 a5 a2 bef2# a14 a10 a17 a4 a1 a16 sa dq6 dq1 v ss a0 nc dq15 dq13 dq4 dq3 dq9 oe# nc v ss dq7 dq12 v dds v ddf dq10 dq0 bes1# dq14 dq5 cios dq11 dq2 dq8 a b c d e f g h sst34hf3223b/3243b 8 7 6 5 4 3 2 1 top view (balls facing down) 543 ill f03.0 a11 a8 we# wp# lbs# a7 a15 a12 a19 bes2 rst# ubs# a6 a3 nc a13 a9 a20 ry/by# a18 a5 a2 nc a14 a10 a17 a4 a1 a16 sa dq6 dq1 v ss a0 nc dq15 dq13 dq4 dq3 dq9 oe# bef# v ss dq7 dq12 v dds v ddf dq10 dq0 bes1# dq14 dq5 cios dq11 dq2 dq8 a b c d e f g h sst34hf322x/324x 8 7 6 5 4 3 2 1 top view (balls facing down)
8 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 table 2: p in d escription symbol pin name functions a ms 1 to a 0 address inputs to provide flash address, a 19 -a 0 . to provide sram address, a 16 -a 0 for 2m and a 17 -a 0 for 4m sa address input (sram) to provide sram address input in byte mode (x8). when cios is v il , the sram is in byte mode and sa provides the most significant address input. when cios is v ih , the sram is in word mode and sa becomes a ?don?t care? pin. dq 15 - dq 0 data inputs/outputs to output data during read cycles and receive input data during write cycles. data is inter- nally latched during a flash erase/program cycle. the outputs are in tri-state when oe# is high or bes1# is high/bes2 is low, and bef# (bef1# and bef2#) is high. bef1# flash memory bank 1 enable to activate the flash memory bank 1 when bef1# is low bef2# flash memory bank 2 enable to activate the flash memory bank 2 when bef2# is low bes1# sram memory bank enable to activate the sram memory bank when bes1# is low bes2 sram memory bank enable to activate the sram memory bank when bes2 is high oe# output enable to gate the data output buffers we# write enable to control the write operations ubs# upper byte control (sram) to enable dq 15 -dq 8 lbs# lower byte control (sram) to enable dq 7 -dq 0 cios i/o configuration (sram) cios = v ih is word mode (x16), cios = v il is byte mode (x8) wp# write protect to protect and unprotect sectors fr om erase or program operation (for bank 1 only) rst# reset to reset and return the device to read mode ry/by# ready/busy# to output the status of the program or erase operation (for bank 2 only). ry/by# is an open drain output, so a 10k ? -100k ? pull-up resistor is required to allow ry/by# to transition high indicating the device is ready to read. v ss ground v dd f power supply (flash) power supply to flash only (2.7-3.3v) v dd s power supply (sram) power supply to sram only (2.7-3.3v) nc no connection unconnected pins t2.3 543 1. a ms = most significant address
preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b 9 ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 . table 3: o perational m odes s election mode bef# 1 bes1# bes2 2 cios 3 oe# we# sa lbs# ubs# dq 7-0 dq 15-8 flash read v il v ih x 4 xv il v ih xx x d out d out xv il flash write v il v ih x x v ih v il xx x d in d in xv il flash erase v il v ih xx v ih v il xx x x x xv il sram read v ih v il v ih v ih v il v ih xv il v il d out d out xv ih v il high-z d out xv il v ih d out high-z v ih v il v ih v il v il v ih sa x x d out high-z sram write v ih v il v ih v ih xv il xv il v il d in d in xv ih v il high-z d in xv il v ih d in high-z v ih v il v ih v il xv il sa x x d in high-z full standby v ih v ih x x x x x x x high-z high-z xv il xxxxx x output disable v ih v il v ih x v ih v ih x x x high-z high-z v il v ih v ih v il v ih xv ih v ih v il v ih xxv ih v ih x x x high-z high-z xv il product identification v il v ih x x v il v ih x x x manufacturer?s id 5 software mode x v il device id 5 t3.0 543 1. bef# = bef1# for operations that apply to flash bank 1. bef# = bef2# for operations that apply to flash bank 2. 2. do not apply bef# = v il , bes1# = v il and bes2 = v ih at the same time 3. sram i/o configuration input cios; v ih = x16 (word mode), v il = x8 (byte mode) 4. x can be v il or v ih , but no other value. 5. with a 19 -a 1 =0; sst manufacturer?s id = 00bfh, is read with a 0 = 0, sst34hf3223b device id = 2761h, is read with a 0 = 1. sst34hf3243b device id = 2761h, is read with a 0 = 1.
10 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 table 4: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 5555h aah 2aaah 55h 5555h a0h wa 3 data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 30h block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x 4 50h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 5 5555h aah 2aaah 55h 5555h 90h software id exit 5,6 5555h aah 2aaah 55h 5555h f0h t4.2 543 1. address format a 14 -a 0 (hex), address a 19 -a 15 can be v il or v ih , but no other value, for command sequence. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for command sequence. 3. wa = program word address. 4. sa x for sector-erase; uses a 19 -a 11 address lines. ba x for block-erase; uses a 19 -a 15 address lines. 5. the device does not remain in software product identification mode if powered down. 6. with a 20 -a 1 = 0; sst manufacturer?s id = 00bfh, is read with a 0 = 0 sst34hf3223b/3243b device id = 2761h, is read with a 0 = 1. absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +125c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd + 0.3v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd + 1.0v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w output short circuit current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma o perating r ange range ambient temp v dd commercial 0c to +70c 2.7-3.3v extended -20c to +85c 2.7-3.3v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 20 and 21
preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b 11 ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 note: bef# = bef1# for operations that apply to flash bank 1. bef2# for operations that apply to flash bank 2. table 5: dc o perating c haracteristics (v dd 1 = 2.7-3.3v) symbol parameter limits test conditions min max units i dd active v dd current address input = v il /v ih , at f=1/t rc min, v dd =v dd max, all dqs open read flash 35 ma oe#=v il , we#=v ih bef#=v il , bes1#=v ih or bes2 = v il sram 20 ma bef#=v ih , bes1#=v il , bes2 = v ih concurrent operation 60 ma bef#=v ih , bes#=v il write 2 flash 40 ma we#=v il bef#=v il , bes1#=v ih or bes2 = v il, oe#=v ih sram 20 ma bef#=v ih , bes1#=v il, bes2 = v ih i sb standby v dd current 3.0v 3.3v 40 75 a a v dd = v dd max, bef#=bes1#=v ihc bes2 = v ilc i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v ih input high voltage 0.7 v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v olf flash output low voltage 0.2 v i ol =100 a, v dd =v dd min v ohf flash output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min v ols sram output low voltage 0.4 i ol =1 ma, v dd =v dd min v ohs sram output high voltage 2.2 v i oh =-500 a, v dd =v dd min t5.4 543 1. v dd = v ddf and v dds 2. i dd active while erase or program is in progress.
12 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 table 6: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read power-up to read operation 100 s t pu-write power-up to write operation 100 s t6.0 543 table 7: c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. i/o pin capacitance v i/o = 0v 24 pf c in 1 input capacitance v in = 0v 12 pf t7.0 543 table 8: f lash r eliability c haracteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t8.0 543
preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b 13 ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 ac characteristics table 9: sram r ead c ycle t iming p arameters symbol parameter sst34hf3223b/3243b-70 sst34hf3223b/3243b-90 units min max min max t rcs read cycle time 70 90 ns t aas address access time 70 90 ns t bes bank enable access time 70 90 ns t oes output enable access time 35 45 ns t byes ubs#, lbs# access time 70 90 ns t blzs 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. bank enable to active output 0 0 ns t olzs 1 output enable to active output 0 0 ns t bylzs 1 ubs#, lbs# to active output 0 0 ns t bhzs 1 bank enable to high-z output 25 35 ns t ohzs 1 output disable to high-z output 25 35 ns t byhzs 1 ubs#, lbs# to high-z output 35 45 ns t ohs output hold from address change 10 10 ns t9.0 543 table 10: sram w rite c ycle t iming p arameters symbol parameter sst34hf3223b/3243b-70 sst34hf3223b/3243b-90 units min max min max t wcs write cycle time 70 90 ns t bws bank enable to end-of-write 60 80 ns t aws address valid to end-of-write 60 80 ns t asts address set-up time 0 0 ns t wps write pulse width 60 80 ns t wrs write recovery time 0 0 ns t byws ubs#, lbs# to end-of-write 60 80 ns t odws output disable from we# low 30 40 ns t oews output enable from we# high 0 0 ns t dss data set-up time 30 40 ns t dhs data hold from write time 0 0 ns t10.0 543
14 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 table 11: f lash r ead c ycle t iming p arameters v dd = 2.7-3.3v symbol parameter sst34hf3223b/3243b-70 sst34hf3223b/3243b-90 units min max min max t rc read cycle time 70 90 ns t ce chip enable access time 70 90 ns t aa address access time 70 90 ns t oe output enable access time 35 45 ns t clz 1 ce# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t chz 1 ce# high to high-z output 20 30 ns t ohz 1 oe# high to high-z output 20 30 ns t oh 1 output hold from address change 0 0 ns t rp 1 rst# pulse width 500 500 ns t rhr 1 rst# high before read 50 50 ns t ry 1,2 rst# pin low to read mode 150 150 s t11.6 543 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. 2. this parameter applies to sector-erase, block-erase, and pr ogram operations. this parameter does not apply to chip-erase. table 12: f lash p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp word-program time 20 s t as address setup time 0 ns t ah address hold time 40 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 2 2. chip-erase operation needs to be done to each individual bank (bef1# and bef2#). 100 ms t by 1,3 3. this parameter applies to sector-erase, block-erase, and pr ogram operations. this parameter does not apply to chip-erase. ry/by# delay time 90 ns t br 1 bus recovery time 1 s t12.6 543
preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b 15 ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 4: sram r ead c ycle t iming d iagram addresses a mss-0 dq 15-0 ubs#, lbs# a mss = most significant sram address oe# bes1# bes2 t rcs t aas t bes t oes t blzs t olzs t byes t bylzs t byhzs data valid t ohzs t bhzs t ohs 543 ill f04.0 t bes
16 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 5: sram w rite c ycle t iming d iagram (we# c ontrolled ) 1 t aws addresses a mss-0 bes1# bes2 we# ubs#, lbs# notes: 1. if oe# is high during the write cycle, the outputs will remain at high impedance. 2. if bes1# goes low or bes2 goes high coincident with or after we# goes low, the output will remain at high impedance. if bes1# goes high or bes2 goes low coincident with or before we# goes high, the output will remain at high impedance. because din signals may be in the output state at this time, input signals of reverse polarity must not be applied. t wps t wrs t wcs t asts t bws t bws t byws t odws t oews t dss t dhs 543 ill f05.0 note 2 note 2 dq 15-8, dq 7-0 valid data in
preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b 17 ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 6: sram w rite c ycle t iming d iagram (ubs#, lbs# c ontrolled ) 1 addresses a mss-0 we# bes1# bes2 t bws t bws t aws t wcs t wps t wrs t asts t byws dq 15-8, dq 7-0 valid data in note 2 note 2 t dss t dhs ubs#, lbs# notes: 1. if oe# is high during the write cycle, the outputs will remain at high impedance. 2. because din signals may be in the output state at this time, input signals of reverse polarity must not be applied. 543 ill f06.0
18 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 7: f lash r ead c ycle t iming d iagram figure 8: f lash we# c ontrolled w ord -p rogram c ycle t iming d iagram 543 ill f07.0 address a 19-0 dq 15-0 we# oe# bef# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 543 ill f32.1 address a 19-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs t by bef# ry/by# 5555 2aaa 5555 addr xxaa xx55 xxa0 data word (addr/data) oe# we# t br t bp note: x can be v il or v ih , but no other value. valid
preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b 19 ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 9: f lash bef# c ontrolled w ord -p rogram c ycle t iming d iagram figure 10: f lash d ata # p olling t iming d iagram valid 543 ill f33.1 address a 19-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# 5555 2aaa 5555 addr xxaa xx55 xxa0 data word (addr/data) oe# bef# t bp t by ry/by# t br note: x can be v il or v ih , but no other value. 543 ill f34.0 address a 19-0 dq 7 data# data# valid data we# oe# bef# t oeh t oe t ce t oes t br
20 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 11: f lash t oggle b it t iming d iagram figure 12: f lash we# c ontrolled c hip -e rase t iming d iagram 543 ill f35.1 address a 19-0 dq 6 we# oe# bef# t oe t oeh t ce two read cycles with same outputs valid data t br valid t br 543 ill f36.2 address a 19-0 dq 15-0 we# 5555 2aaa 2aaa 5555 5555 xx55 xx10 xx55 xxaa xx80 xxaa 5555 oe# bef# six-byte code for chip-erase t sce t wp note: this device also supports bef# controlled chip-erase operation. the we# and bef# signals are interchageable as long as minimum timings are met. (see table 12) x can be v il or v ih , but no other value. t by ry/by#
preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b 21 ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 13: f lash we# c ontrolled b lock -e rase t iming d iagram figure 14: f lash we# c ontrolled s ector -e rase t iming d iagram 543 ill f37.2 address a 19-0 dq 15-0 we# 5555 2aaa 2aaa 5555 5555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# bef# six-byte code for block-erase t wp note: this device also supports bef# controlled block-erase operation. the we# and bef# signals are interchageable as long as minimum timings are met. (see table 12) ba x = block address x can be v il or v ih , but no other value. t by ry/by# valid t br t be 543 ill f38.2 address a 19-0 dq 15-0 we# 5555 2aaa 2aaa 5555 5555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# bef# six-byte code for sector-erase t se t wp note: this device also supports bef# controlled sector-erase operation. the we# and bef# signals are interchageable as long as minimum timings are met. (see table 12) sa x = sector address x can be v il or v ih , but no other value. t by ry/by# valid t br
22 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 15: f lash s oftware id e ntry and r ead figure 16: cfi e ntry and r ead 543 ill f39.1 address a 14-0 t ida dq 15-0 we# 5555 2aaa 5555 0000 0001 oe# bef# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 device id = 2761h for sst34hf3223b and 2761h for sst34hf3243b note: x can be v il or v ih , but no other value. 543 ill f30.1 address a 14-0 t ida dq 15-0 we# 5555 2aaa 5555 oe# bef# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx98 note: x can be v il or v ih , but no other value.
preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b 23 ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 17: f lash s oftware id e xit /cfi e xit figure 18: rst# t iming d iagram ( when no internal operation is in progress ) 543 ill f15.2 address a 14-0 dq 15-0 t ida t wp t whp we# 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# bef# xxaa xx55 xxf0 note: x can be v il or v ih , but no other value. 543 ill f40.1 ry/by# 0v rst# bef#/oe# t rp t rhr
24 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 19: rst# t iming d iagram ( during s ector - or b lock -e rase operation ) figure 20: ac i nput /o utput r eference w aveforms figure 21: a t est l oad e xample 543 ill f41.1 ry/by# bef# oe# t rp t ry t br rst# 543 ill f19.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 543 ill f20.0 to tester to dut c l
preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b 25 ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 22: w ord -p rogram a lgorithm 543 ill f21.0 start load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xxa0h address: 5555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value.
26 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 23: w ait o ptions 543 ill f22.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b 27 ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 24: s oftware p roduct id/cfi c ommand f lowcharts 543 ill f23.1 load data: xxaah address: 5555h software product id entry command sequence load data: xx55h address: 2aaah load data: xx90h address: 5555h wait t ida read software id load data: xxaah address: 5555h cfi query entry command sequence load data: xx55h address: 2aaah load data: xx98h address: 5555h wait t ida read cfi data load data: xxaah address: 5555h software id exit/cfi exit command sequence load data: xx55h address: 2aaah load data: xxf0h address: 5555h wait t ida return to normal operation note: x can be v il or v ih, but no other value.
28 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 figure 25: e rase c ommand s equence 543 ill f24.0 load data: xxaah address: 5555h chip-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx10h address: 5555h load data: xxaah address: 5555h wait options 1 chip erased to ffffh load data: xxaah address: 5555h sector-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx30h address: sa x load data: xxaah address: 5555h wait options 1 sector erased to ffffh load data: xxaah address: 5555h block-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx50h address: ba x load data: xxaah address: 5555h wait options 1 block erased to ffffh note: x can be v il or v ih, but no other value. refer to figure 23
preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b 29 ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 product ordering information valid combinations for sst34hf3223b sst34hf3223b-70-4c-lp SST34HF3223B-90-4C-LP sst34hf3223b-70-4e-lp sst34hf3223b-90-4e-lp valid combinations for sst34hf3243b sst34hf3243b-70-4c-lp sst34hf3243b-90-4c-lp sst34hf3243b-70-4e-lp sst34hf3243b-90-4e-lp note: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations. device speed suffix1 suffix2 sst34 h f32 x 3 b -xxx -x x -x x package modifier p = 56 pins package type l = lfbga (10mm x 12mm x 1.4mm) temperature range c = commercial = 0c to +70c e = extended = -20c to +85c minimum endurance 4 =10,000 cycles read access speed 70 = 70 ns 90 = 90 ns version bank split 3 = 16 mbit (12+4) + 16 mbit (12+4). total 4 banks. sram density 0 = no sram 2 = 2 mbit 4 = 4 mbit flash density 32 = 32 mbit voltag e h = 2.7-3.3v device family 34 = csf + sram combomemory
30 preliminary information 32 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf3223b / sst34hf3243b ?2002 silicon storage technology, inc. s71197-00-000 1/02 543 packaging diagrams 56- ball l ow - profile , f ine - pitch b all g rid a rray (lfbga) 10 mm x 12 mm (64 possible ball positions ) sst p ackage c ode : lp a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 8 7 6 5 4 3 2 1 seating plane 0.35 0.05 1.30 0.10 0.15 10.00 0.20 0.45 0.05 (56x) a1 corner 12.00 0.20 0.80 5.60 0.80 5.60 56ba-lfbga-lp-10x12-450mic-ill.2 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registered. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (.05) mm. 4. the actual shape of the corners may be slightly different than as portrayed in the drawing. 8 7 6 5 4 3 2 1 1mm silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com

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